1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a power-on resetting circuit.
2. Description of the Related Art
In general, semiconductor integrated circuits implement a power-on resetting circuit. When the power supply is switched on, the power-on resetting circuit is operated to initialize internal circuits, which avoids malfunctions of the semiconductor integrated circuit.
FIG. 1 shows the waveform of a power-on resetting signal POR which a power-on resetting circuit of this type generates. Hereinafter, the power-on resetting signal POR will be sometimes simply referred to as reset signal POR.
When an external supply voltage VCC starts being supplied to the semiconductor integrated circuit, the reset signal POR follows the external supply voltage VCC to rise in level for a predetermined period, and then changes to low level (inactivation). Internal circuits necessary to be initialized in the semiconductor integrated circuit are initialized during a period T1 from the supply voltage VCC reaching a predetermined value to the reset signal POR being inactivated. Then, the inactivation (low level) of the reset signal POR terminates the reset operation, whereby the internal circuits start their normal operations.
This kind of power-on resetting circuit typically utilizes threshold voltage of a transistor to detect the rise of the supply voltage VCC up to the predetermined value and inactivate the reset signal POR.
Recently, semiconductor integrated circuits have lowered in operation voltage. The supply voltage VCC supplied from exterior has also lowered. The threshold voltage of the transistor has little dependence on the supply voltage VCC, and thus the ratio of the threshold voltage of the transistor to the supply voltage VCC becomes higher. As a result, power-on resetting circuits vary greatly in the detection level of the supply voltage VCC, due to fluctuations in the threshold voltage. The amount of deviation (T2 in FIG. 1) in the inactivation timing of the reset signal POR has a greater effect on the variations of the threshold voltage than in higher operation voltage. The threshold voltage of the transistor fluctuates with variations in the manufacturing conditions of the semiconductor integrated circuit, as well as the position of the chip on the wafer and the position of the wafer in the manufacturing lot.
For example, when the inactivation timing of the reset signal POR advances, the reset period T1 will be short. This may hamper normal initialization of the internal circuits. At the worst, the high-level period of the reset signal POR, necessary for initializing internal circuit, might be almost none. Meanwhile, when the inactivation timing of the reset signal POR delays, the reset signal POR might not be inactivated (kept high level). Furthermore, when the inactivating timing of the reset signal POR is inappropriate, transient fluctuations in the supply voltage VCC or the ground voltage possibly cause the power-on resetting circuit to malfunction, thereby activating the reset signal POR temporarily.
Moreover, in the cases of directly measuring the inactivation timing of the reset signal POR, the inactivation timing substantially varies due to a contact with a tester probe. In order to avoid this, it is necessary to add an output element (testing circuit), which requires an additional layout area. Besides, the evaluation by using a testing circuit is generally performed after semiconductor integrated circuits are entered into a test mode. However, the presence of the circuits to be initialized by the reset signal POR on the signal path related to the testing circuit makes the entering to the test mode impossible, thereby precluding the evaluation itself.
An object of the present invention is to reduce variations in the inactivation timing of the reset signal generated by the power-on resetting circuit.
Another object of the present invention is to operate the power-on resetting circuit with reliability and initialize an internal circuit even when the external supply voltage is low.
According to one aspect of the present invention, a semiconductor integrated circuit has a power-on resetting circuit for activating a reset signal which initializes an internal circuit, for a predetermined period after a power supply is switched on, and then inactivating the reset signal. The inactivation timing of the reset signal is changed by a timing changing circuit. Therefore, the inactivation timing which has deviated due to fluctuations in the manufacturing conditions of the semiconductor integrated circuit can be adjusted to a normal value. This consequently allows reliable initialization of the internal circuit.
According to another aspect of the present invention, the inactivation timing is changed corresponding to a threshold voltage of transistors implemented in the internal circuit. In general, the power-on resetting circuit utilizes the threshold voltage of the transistors to generate the reset signal. Here, the inactivation timing depends on the threshold voltage. Changing the inactivation timing corresponding to the threshold voltage of the transistors implemented makes it possible that the timing changing circuit optimally adjusts the inactivation timing of the reset signal. That is, the inactivation timing can be optimized based on the threshold voltage.
Even when a supply voltage supplied from exterior is low, and the ratio of the threshold voltage of the transistors to the supply voltage is high, the power-on resetting circuit operates with reliability to generate the reset signal. This allows initialization of the internal circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a voltage generator for generating an internal supply voltage different from an external supply voltage in accordance with the external supply voltage supplied from exterior. The timing changing circuit easily changes the inactivation timing of the reset signal by utilizing the internal supply voltage which varies with a threshold voltage of transistors implemented in the voltage generator.
According to another aspect of the semiconductor integrated circuit in the present invention, the timing changing circuit has a programming circuit having a fuse. The inactivation timing of the reset signal is changed by programming the fuse in correspondence with the internal supply voltage. Once the inactivation timing is set, it will remain unchanged, therefore, the inactivation timing can be surely adjusted in the manufacturing process of the semiconductor integrated circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit has a testing circuit for changing the internal supply voltage. Then, the fuse to be programmed is determined for the sake of optimizing the inactivation timing based on the operation of the testing circuit. For example, in the testing process of semiconductor integrated circuits, the testing circuit on each chip (semiconductor integrated circuit) is initially operated to check the optimum inactivation timing. Subsequently, the optimum inactivation timing can be set for each chip by programming the corresponding fuse.
According to another aspect of the semiconductor integrated circuit in the present invention, the internal supply voltage is adjusted to a predetermined value simultaneously with the change of the inactivation timing of the reset signal, by programming the fuse. This allows the fuse for setting the inactivation timing and the internal supply voltage to be shared when both the inactivation timing and the internal supply voltage depend on the threshold value. Fuses to be blown by laser beam irradiation require greater areas. Thus, the sharing of fuses is effective for a reduction in chip size.